这个名字代表“Many-core Integrated Accelerator Of the Waterdeep”，是基于AMD Southern Islands Radeon HD 6000系列显卡开源指令集架构的电阻-晶体管逻辑实现。
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MIAOW (pronounced "me-ow") [Many-core Integrated Accelerator Of Waterdeep/Wisconsin] is an open source GPU created by the Vertical Research Group at the University of Wisconsin-Madison led by Professor Karu Sankaralingam. Based off of the publicly released Southern Islands ISA by AMD, MIAOW implements a compute unit suitable for performing architecture analysis and experimentation with GPGPU workloads. In addition to the Verilog HDL composing the compute unit, MIAOW also includes a suite of unit tests and benchmarks for regression testing.
A primary motivator for MIAOW's creation is the belief that software simulators of hardware such as CPUs and GPUs often miss many subtle aspects that can skew the performance, power, and other quantitative results that they produce. As an actual implementation of a GPU's logic, the Vertical Research Group believes that MIAOW can be a useful tool in producing not only more accurate quantitative results when benchmarking GPGPU workloads but also provide context for the architectural complexities of actually implementing newly proposed algorithms and designs that are intended to improve performance or other desired characteristics.
It must be emphasized that MIAOW represents a GPU's compute unit. It does not possess the auxiliary logic required to produce actual graphical output nor does it have logic to connect it to a specific memory interface or system bus. These extensions can be developed and we would welcome outside contributors for such efforts, but as MIAOW was created as a research tool their presence was not an absolute necessity in running benchmarks and experiments.
MIAOW is licensed under the 3-clause BSD license
MIAOW is being released in phases as we complete the necessary preparation and packaging. Be sure to check this section to see what has been made available and what we hope to make available in the near future.
RTL implementation of MIAOW compute unit
Testbench for verification
Benchmarks (instruction and data traces) that are known to run on MIAOW (derived from AMD APP SDK)
FPGA bootstrapping framework
Synthesis scripts for area and power analysis
Verilog for hardware dispatcher for controlling multiple CUs
Patch for multi2sim simulator to generate reference instruction traces
Case Studies Documentation
Nyuzi is an experimental multicore GPGPU processor. It supports vector floating point, hardware multithreading, and cache coherence. The SystemVerilog-based hardware implementation is synthesizable and runs on FPGA. This project also includes an LLVM-based C++ toolchain, tests, and other tools. It is useful for microarchitecture experimentation, performance modeling, and parallel software development.
Mailing list: https://groups.google.com/forum/#!forum/nyuzi-processor-dev
License: Apache 2.0
GPUs have proven useful for applications with a lot of inherent parallelism like image processing and machine learning. However, GPUs have a highly constrained programming model that lacks flexibility. This project is a hybrid architecture that combines GPU architectural concepts like wide SIMD and hardware multithreading with a general purpose instruction set. The hardware implementation is focused more on computation than graphics, lacking fixed function graphics hardware. It is capable of operating as a coprocessor or a standalone processor.
This has been synthesized using the Nangate 45nm cell library. Estimates per core: area 1.84 mm2, power 329 mW, maximum frequency 671 Mhz.